1. Field of the Invention
This invention relates to a driving device driving a solid-state image pickup device such as a charge coupled device (CCD) or the like and, more particularly, to a driving device capable of changing a driving capability of the CCD (the solid-state image pickup device).
2. Description of Related Art
Various driving device capable of changing the driving capability of the solid-state image pickup device such as the CCD are already proposed heretofore.
By way of illustration, JP 2002-27333 A (which will later be called Patent Document 1) discloses a “driving device of a solid-state image pickup device” in which an output portion for horizontal CCD driving pulses of a which is configured by connecting to parallel with n (plural) 3-state buffers. In the driving device disclosed in Patent Document 1, a driving capacity of the horizontal CCD driving pulses produced by the output portion is changed by controlling states of respective 3-state buffers by control lines in accordance with a terminal load capacity of the CCD solid-state pickup device, respectively.
Although the states of the 3-state buffers are controlled by the control lines in the driving device disclosed in Patent Document 1, Patent Document 1 never discloses a method of controlling the control lines. In addition, inasmuch as the control lines are directly connected to the respective 3-state buffers in the driving device to control the respective 3-state buffers in the driving device disclosed in Patent Document 1, a lot of control lines are required to control on/off of the respective 3-state buffers.
In addition, JP 2004-248003 A (which will later be called Patent Document 2 and which corresponds to US 2004/0183920 A1) discloses an “image capturing device” including a driving circuit configured with a first inverter, an OR gate, an AND gate, a second inverter, a first transistor, and a second transistor. The first inverter inverts a timing signal supplied from a timing control circuit to supply an inverted timing signal from a first node to a solid-state image pickup device as a driving clock signal. The first transistor comprises a P-channel MOS transistor and is connected between a power supply and a second node. The second transistor comprises an N-channel MOS transistor and is connected between a ground point and a second node. The second inverter inverts a configuration value to produce an inverted configuration value. The OR gate ORs the timing signal and the inverted configuration value to supply an ORed output to a gate of the first transistor. The AND gate ANDs the timing signal ant the inverted configuration value to supply an ANDed output to a gate of the second transistor. Although the driving circuit comprises a circuit in a case of two-stage switching of driving capabilities, the driving capabilities can be switched at a larger number of stages through three or more structures connected in parallel to the first inverter, each including the OR gate, the AND gate, the second inverter, and the first and second transistors.
It is necessary for an image capturing device disclosed in Patent Document 2 to connect the structure including the OR gate, the AND gate, the second inverter, and the first and second transistors in parallel to the first inverter in three or more stages in order to increase the number of selected stages, a component count is increased in accordance with the number of stages. In addition, the configuration values must be set every structure including the OR gate, the AND gate, the second inverter, and the first and second transistors in the image capturing device disclosed in Patent Document 2, a lot of configuration values are required to increase the number of stages.
JP 2006-108757 A (which will later be called Patent Document 3) discloses a “CCD driving circuit” for which cost reduction and shortening of time for design can be realized by commonly using a circuit for a plurality of CCD image sensors having different driving performance. The CCD driving circuit disclosed in Patent Document 3 comprises a driving signal generator for generating a driving signal to be produced to a CCD image sensor, a driving performance information acquiring section for acquiring CCD driving performance information, and a control unit for causing the driving signal generator to generate a driving signal consisting of driving performance corresponding to the driving performance information acquired by the driving performance information acquiring section. The diving signal generator comprises a plurality of driving signal generating circuits each of which comprises a tri-state buffer or the like. The driving signal generating circuits are connected to in parallel with each other. The control unit causes the driving signal generating circuits in the driving signal generator to generate that are equal in number to the number indicated by the driving performance information. Outputs of the driving signal generating circuits driven are collected to supply to the CCD image sensor as a driving signal.
In the CCD driving circuit disclosed in Patent Document 3, turning on/off of the tri-state buffers (the driving signal generating circuits) is carried out by using select signals produced by the control unit. As a results, a lot of select signals are required in the CCD driving circuit disclosed in Patent Document 3 also in order to control the on/off of the respective tri-state buffers (the driving signal generating circuits) in the manner which is similar to a case of the above-mentioned Patent Document 1.
JP 2007-336300 A (which will later be called Patent Document 4) discloses an “imaging apparatus” which is capable of achieving optimization of power consumption. The imaging apparatus disclosed in Patent Document 4 comprises a solid-state imaging element for imaging an optical image of an object as an electrical signal, a timing pulse generation circuit for producing a driving signal for reading the electrical signal to the solid-state imaging element, and a CPU for controlling driving capability (driving current) of the driving signal produced by the timing pulse generation circuit in accordance with an operating state of the imaging apparatus.
In the imaging apparatus disclosed in Patent Document 4, the CPU sets a driving current value (control data) to the timing pulse generation circuit and the timing pulse generation circuit drives the solid-state imaging element at a set driving current value. However, Patent Document 4 never discloses a concrete circuit configuration of the timing pulse generation circuit.